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<a href="#define-members">Macros</a> &#124;
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Macros</h2></td></tr>
<tr class="memitem:ga02055aef4b0f9a801005ebdc7b556157"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__api.html#ga02055aef4b0f9a801005ebdc7b556157">MAX_DELAY_CNT</a>&#160;&#160;&#160;1000000000U</td></tr>
<tr class="memdesc:ga02055aef4b0f9a801005ebdc7b556157"><td class="mdescLeft">&#160;</td><td class="mdescRight">Max delay count.  <a href="group__qspipsu__api.html#ga02055aef4b0f9a801005ebdc7b556157">More...</a><br/></td></tr>
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Functions</h2></td></tr>
<tr class="memitem:ga803eccd67d1dfde416b54488865c1e9d"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__api.html#ga803eccd67d1dfde416b54488865c1e9d">XQspiPsu_CfgInitialize</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr, const <a class="el" href="struct_x_qspi_psu___config.html">XQspiPsu_Config</a> *ConfigPtr, UINTPTR EffectiveAddr)</td></tr>
<tr class="memdesc:ga803eccd67d1dfde416b54488865c1e9d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initializes a specific <a class="el" href="struct_x_qspi_psu.html" title="The XQspiPsu driver instance data. ">XQspiPsu</a> instance as such the driver is ready to use.  <a href="group__qspipsu__api.html#ga803eccd67d1dfde416b54488865c1e9d">More...</a><br/></td></tr>
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<tr class="memitem:ga46a8ddc9fc0b6f9e2d616de84d9c7ed5"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__api.html#ga46a8ddc9fc0b6f9e2d616de84d9c7ed5">XQspiPsu_Idle</a> (const <a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga46a8ddc9fc0b6f9e2d616de84d9c7ed5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stops the transfer of data to internal DST FIFO from stream interface and also stops the issuing of new write commands to memory.  <a href="group__qspipsu__api.html#ga46a8ddc9fc0b6f9e2d616de84d9c7ed5">More...</a><br/></td></tr>
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<tr class="memitem:ga799b60ee7157ed46b84475677aa0dc03"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__api.html#ga799b60ee7157ed46b84475677aa0dc03">XQspiPsu_Reset</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga799b60ee7157ed46b84475677aa0dc03"><td class="mdescLeft">&#160;</td><td class="mdescRight">Resets the QSPIPSU device.  <a href="group__qspipsu__api.html#ga799b60ee7157ed46b84475677aa0dc03">More...</a><br/></td></tr>
<tr class="separator:ga799b60ee7157ed46b84475677aa0dc03"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaa69ec6da90deb760954ea3dcfd55d7f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__api.html#gaaa69ec6da90deb760954ea3dcfd55d7f">XQspiPsu_Abort</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaaa69ec6da90deb760954ea3dcfd55d7f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Aborts a transfer in progress.  <a href="group__qspipsu__api.html#gaaa69ec6da90deb760954ea3dcfd55d7f">More...</a><br/></td></tr>
<tr class="separator:gaaa69ec6da90deb760954ea3dcfd55d7f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5f083afb4ec79c542a7c7098a519d771"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__api.html#ga5f083afb4ec79c542a7c7098a519d771">XQspiPsu_PollDataHandler</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr, u32 StatusReg)</td></tr>
<tr class="memdesc:ga5f083afb4ec79c542a7c7098a519d771"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is the handler for polling functionality of controller.  <a href="group__qspipsu__api.html#ga5f083afb4ec79c542a7c7098a519d771">More...</a><br/></td></tr>
<tr class="separator:ga5f083afb4ec79c542a7c7098a519d771"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga61de390e2bc4af0ce77448a46763ea39"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__api.html#ga61de390e2bc4af0ce77448a46763ea39">XQspiPsu_PolledTransfer</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr, <a class="el" href="struct_x_qspi_psu___msg.html">XQspiPsu_Msg</a> *Msg, u32 NumMsg)</td></tr>
<tr class="memdesc:ga61de390e2bc4af0ce77448a46763ea39"><td class="mdescLeft">&#160;</td><td class="mdescRight">Performs a transfer on the bus in polled mode.  <a href="group__qspipsu__api.html#ga61de390e2bc4af0ce77448a46763ea39">More...</a><br/></td></tr>
<tr class="separator:ga61de390e2bc4af0ce77448a46763ea39"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ae727534cf55b878b9b1974dc72a625"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__api.html#ga6ae727534cf55b878b9b1974dc72a625">XQspiPsu_InterruptTransfer</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr, <a class="el" href="struct_x_qspi_psu___msg.html">XQspiPsu_Msg</a> *Msg, u32 NumMsg)</td></tr>
<tr class="memdesc:ga6ae727534cf55b878b9b1974dc72a625"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initiates a transfer on the bus and enables interrupts.  <a href="group__qspipsu__api.html#ga6ae727534cf55b878b9b1974dc72a625">More...</a><br/></td></tr>
<tr class="separator:ga6ae727534cf55b878b9b1974dc72a625"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa345ea3ab3694a94a60e6217cb8d5e59"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__api.html#gaa345ea3ab3694a94a60e6217cb8d5e59">XQspiPsu_InterruptHandler</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaa345ea3ab3694a94a60e6217cb8d5e59"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handles interrupt based transfers by acting on GENFIFO and DMA interurpts.  <a href="group__qspipsu__api.html#gaa345ea3ab3694a94a60e6217cb8d5e59">More...</a><br/></td></tr>
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<tr class="memitem:ga02ea5e95c8939c2be78d26c255a6ba6f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__api.html#ga02ea5e95c8939c2be78d26c255a6ba6f">XQspiPsu_SetStatusHandler</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr, void *CallBackRef, <a class="el" href="group__qspipsu__api.html#ga4fcad0707fd0557232bc94a8c3ba1fea">XQspiPsu_StatusHandler</a> FuncPointer)</td></tr>
<tr class="memdesc:ga02ea5e95c8939c2be78d26c255a6ba6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to upper layer software.  <a href="group__qspipsu__api.html#ga02ea5e95c8939c2be78d26c255a6ba6f">More...</a><br/></td></tr>
<tr class="separator:ga02ea5e95c8939c2be78d26c255a6ba6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ec97b3d7c6cb24544f0bfa8114b56d7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__api.html#ga0ec97b3d7c6cb24544f0bfa8114b56d7">XQspiPsu_WriteProtectToggle</a> (const <a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr, u32 Toggle)</td></tr>
<tr class="memdesc:ga0ec97b3d7c6cb24544f0bfa8114b56d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables/disables Write Protect pin on the flash parts.  <a href="group__qspipsu__api.html#ga0ec97b3d7c6cb24544f0bfa8114b56d7">More...</a><br/></td></tr>
<tr class="separator:ga0ec97b3d7c6cb24544f0bfa8114b56d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga769969b43f91def18f7501555ec35b11"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__api.html#ga769969b43f91def18f7501555ec35b11">XQspiPsu_StartDmaTransfer</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr, <a class="el" href="struct_x_qspi_psu___msg.html">XQspiPsu_Msg</a> *Msg, u32 NumMsg)</td></tr>
<tr class="memdesc:ga769969b43f91def18f7501555ec35b11"><td class="mdescLeft">&#160;</td><td class="mdescRight">Starts a DMA transfer.  <a href="group__qspipsu__api.html#ga769969b43f91def18f7501555ec35b11">More...</a><br/></td></tr>
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<tr class="memitem:ga6be41fd692a96516b0ce22591510c73d"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu__api.html#ga6be41fd692a96516b0ce22591510c73d">XQspiPsu_CheckDmaDone</a> (<a class="el" href="struct_x_qspi_psu.html">XQspiPsu</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga6be41fd692a96516b0ce22591510c73d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Checks for DMA transfer complete.  <a href="group__qspipsu__api.html#ga6be41fd692a96516b0ce22591510c73d">More...</a><br/></td></tr>
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